Delay calculation using 8085 microprocessor

Hello friends
Lets understand the process of delay calculation in 8085 using following example. We need to calculate the exact duration in microseconds or milliseconds which would be provided by given delay routine.

Let's assume that 8085 is running at 2MHz frequency so
1 clock duration (T) = 1/f = 0.5usec

1                 MVI B, 10H     7 T-States
2 LOOP2    MVI C, FFH     7 T-States
3 LOOP1    DCR C              4 T-States
4                 JNZ LOOP1    10 T-States
5                 DCR B              4 T-States
6                 JNZ LOOP2    10 T-States

Now start calculation

NOTE: Always remember to start from inner most loop and then move towards outer loop.

In this program, for sake of simplicity, I have also associated line numbers

Steps:

1) 1st innermost loop is at line no. 3 and 4. Now line 3 and 4 is going to get repeated for FFH or 256 times i.e. (10+4) T-states would be repeated for256 times. But since, in the last itteration, JNZ condition fails and JZ instruction gets executed. JNZ instruction takes 10 T-states whereas JZ takes 7 T-states. So for 14 T-states are processed for 254 iterations, but in 255th iteration, it took only 11 T-states, so while calculation:
  
        (255 x 14) - 3 = 3567 T-states

2) Now, these 3567 T-states, along with (7+4+10) T-states are placed in another outer loop, which is going to rotate for 10H times or 16 times. Don't forget to subtract 3 for the same reason mentioned in point 1.

        ( (3567 + 7 + 4 + 10) x 16) - 3 = 57405 T-states

3) Now, combine this value to the T-state of 1st instruction of delay routine

         (57405+7) = 57412 T-state

4) Since 1 clock duration = 1 T-state = 0.5usec, so

          (57412 x 0.5usec) = 28.706 msec

This given routine is going to generate delay of 28.706 msec. This same process is applied to calculate the execution time of any 8085 microprocessor program such that user can calculate how responsive system might be, if the system is running using given program and said specification.

Happy learning :-) Please post your comments below!

8085 Timing Diagram detailed explaination using example.

Hi friends
What exactly timing diagram tell us?? It tells us the internal behavior of microprocessor while instruction gets processed. Microprocessor generates certain signals from its various pins which could be plotted on oscilloscope and informs user about internal behavior of microprocessor, in response to the instruction getting currently processed.

Lets me talk about 8085 timing diagram using simple example

 

This timing diagram is for one typical instruction MVI A,32H, which is stored at memory location 2000H.What does it mean ?

Every microprocessor instruction is made of opcode and operand. 

Opcode is the equivalent Hex code for instruction mnemonic (ex: for opcode MVI A,8 bit, 3E is an equivalent Hex value). This Hex value is predefined and available in data sheet of microprocessor.

Operand is the 8-bit (data) or 16-bit number (data/address) mentioned in instruction. 

Now, when we write program for microprocessor, these instructions (opcode+operand) get stored in program memory. In our example, opcode 3E get stored at address 2000H and operand 32H get stored at address 2001H. 

Every instruction is made of 1 or few machine cycles (predefined in data-sheet), which is made of T-states. T-states are smallest unit of execution in microprocessor, which is equivalent to 1 clock cycle. 

For this instruction (ex: MVI A,32H), we need 2 machine cycles (M1 and M2). Machine cycle M1 is make of 4 T-states, where 3 T-states are used for opcode fetch from program memory and 1 T-state is used for its decoding. Similarly, Machine cycle M2 is made of 3 T-states which is needed for operand fetch from program memory. We need only 3 T-states in M2 since decoding is not needed for operand whereas opcode need extra 1 T-state for decoding process and converting mnemonic into equivalent Hex code. As I mentioned earlier, 1 T-state = 1clock cycle since T-state is smallest unit of operation in microprocessor.

Looking more deeper in working of instruction, MVI A,32H, very first requirement is to fetch instruction opcode from program memory so appropriate address need to be loaded in processor address buses. Before program memory address is loaded in processor Address Bus, ALE pin should go from LOW-->HIGH. This would actually multiplex the lower order address/data bus (AD7--AD0) so that it would act as Address Bus (A7--A0). Now we can load program memory address of instruction (00H address on A7--A0 and 20H address on A15--A0) on processor address bus.

NOTE: Lower order address bus AD7--AD0 can be used as address bus A7--A0 (when ALE goes LOW-->HIGH) or as data bus (when ALE goes from HIGH -->LOW)   

Working of Timing diagram at T-state level in content to given diagram:

1) In 1st T-state, load lower order address (00H) is loaded in AD7--AD0 and higher order address (20H) is loaded in A15--A8. ALE is maintained HIGH at this instant. Read pin is also maintained HIGH since, no reading is yet to take place (address is just getting loaded right now).

2) During 1st T-state, after address is loaded in address bus, ALE goes from HIGH-->LOW, telling processor to change the state of AD7--AD0 bus to D7--D0 Data Bus after the loaded address (2000H) is identified in entire 64K memory space. This is done so that after memory location 2000H is identified in memory, data can be retrieved in same bus D7-D0.

3) Pins IO/M=0, S1=1 & S2=1 which informs user that "opcode fetch" operation (ex: MVI A,8 bit) is currently getting executed inside microprocessor

4) During 2nd T-state, searching of address 2000H takes place and when the address is found, multiplexing takes place which make AD7--AD0 act as Data Bus D7--D0. Read pin goes from HIGH-->LOW so that reading from required memory location (2000H) could take place in Data Bus. Reading process completes in 3rd T-state, thus, RD signal goes HIGH again.

5) In 4th T-state, both address buses remain in High Impedance state since decoding of opcode take place in Instruction Decoder.

6) By the end of 4th T-state, opcode 3E is fetched from memory location 2000H and decoded. Now fetching of operand 32H need to take place.

7) Again ALE signal goes from LOW-->HIGH, which multiplex lower order address/data bus AD7--AD0 and they start acting as Address Bus A7--A0. Now, address of operand 32H, which is stored at address 2001H, is loaded in Higher order (A15--A8) and Lower order Address Bus (A7--A0) and searching of address (2001H) begins in entire 64K memory range.

8) In 5th T-state, ALE again goes back from HIGH-->LOW, telling processor to use AD7--AD0 as Data Bus after memory location 2001H is identified.

9) Pins IO/M=0, S1=1 and S2=0, thus, informing user that currently, "operand read" process is taking place within microprocessor.

10) When 2001H memory location is identified in program memory, AD7--AD0 start acting as D7--D0 since ALE already goes from HIGH --> LOW. RD signal goes from HIGH-->LOW so that read operation can take place in 6th T-state . Once reading is completed, RD signal again goes back from LOW--> HIGH.

This completes the working explanation of instruction MVI A,32H using timing diagram.

NOTE: Since this instruction is based on simple Data transfer instruction, no actual work is done by instruction i.e. no loading or storing of opcode/data takes place from memory/IO. If any instruction where memory access or I/O access is done, few additional machine cycles would be needed to complete that work.

Hope it would help someone looking for details on 8085 Timing Diagrams

In case of any doubts, lets discuss :-)

Happy learning ! Please post your comments below.